CMOS image sensors are increasingly being used as a low cost alternative to charge coupled device (CCD) image sensors. In a CMOS image sensor, the active elements of a pixel cell perform the necessary functions of: (1) photon to charge conversion; (2) accumulation of image charge; (3) transfer of charge to the sensing node accompanied by charge amplification; (4) resetting the sensing node to a known state before the transfer of charge to it; (5) selection of a pixel for readout; and (6) output and amplification of a signal representing pixel charge from the sensing node.
CMOS image sensors of the type discussed above are generally known as discussed, for example, in Nixon et al., “256×256 CMOS Active Pixel Sensor Camera-on-a-Chip,” IEEE Journal of Solid-State Circuits, Vol. 31(12), pp. 2046-2050 (1996); and Mendis et al., “CMOS Active Pixel Image Sensors,” IEEE Transactions on Electron Devices, Vol. 41(3), pp. 452-453 (1994). Exemplary CMOS image sensor circuits, processing steps thereof, and detailed descriptions of the functions of various CMOS elements of an image sensor circuit are described, for example, in U.S. Pat. Nos. 6,140,630, 6,376,868, 6,310,366, 6,326,652, 6,204,524, and 6,333,205, assigned to Micron Technology, Inc. The disclosures of each of the forgoing patents are herein incorporated by reference in their entirety.
FIG. 1A is schematic diagram of a conventional CMOS pixel cell 1, which includes conventional pixel cells 10. FIG. 1B shows a top plan view of a pixel cell 10 of FIG. 1A, while FIG. 1C shows a cross-sectional view of the pixel cell 10 of FIG. 1B along line 1C-1C′. Typically, the pixel cells 10 are formed at a surface of a substrate 11 (FIG. 1C). A pixel cell 10 is isolated from other pixel cells 10 and peripheral circuitry (not shown) by an isolation region 12 (FIG. 1C), which is shown as a shallow trench isolation (STI) region. The substrate 11 is doped to a first conductivity type, e.g., p-type and is biased at a ground potential.
As is known in the art, a pixel cell 10 functions by receiving photons of light and converting those photons into charge carried by electrons. For this, each one of the pixel cells 10 includes a photo-conversion device 21, which is shown as a pinned photodiode, but can be a non-pinned photodiode, photogate, photoconductor, or other photosensitive device. The photodiode 21 includes an n-type photodiode charge accumulation region 22 and a p-type surface layer 23 (FIG. 1C).
Each pixel cell 10 also includes a transfer transistor 27, which receives a transfer control signal TX at its gate electrode 30b. The transfer transistor 27 is connected to the photodiode 21 and a floating diffusion region 25. During operation, the TX signal operates the transfer transistor 27 to transfer charge from the photodiode charge accumulation region 22 to the floating diffusion region 25.
The pixel cell 10 further includes a reset transistor 28, which receives a reset control signal RST at its gate electrode 30b. The reset transistor 28 is connected to the floating diffusion region 25 and includes a source/drain region 60 coupled to a voltage supply, Vaa-pix, through a contact 61. In response to the RST signal, the reset transistor 28 operates to reset the diffusion region 25 to a predetermined charge level Vaa-pix.
A source follower transistor 29 has a gate electrode 30b coupled to the floating diffusion region 25 through a contact 61 that receives and amplifies a charge level from the diffusion region 25. The source follower transistor 29 also includes a first source/drain region 60 coupled to the power supply voltage, Vaa-pix, and a second source/drain region 60 connected to a row select transistor 26. The row select transistor 26 receives a row select control signal ROW_SEL at its gate electrode 30b. In response to the ROW_SEL signal, the row select transistor 26 couples the pixel cell 10 to a column line 22, which is coupled to a source/drain region 60 of the row select transistor 26. When the row select gate electrode 30b is operated, an output voltage is output from the pixel cell 20 through the column line 22.
As shown in FIG. 1C, the transistor gates 30b are part of gate stacks 30. Although, FIG. 1C shows only the transfer transistor 27 and reset transistor 28 having gate stacks 30, the source follower transistor 29 and the row select transistor 26 also include respective gate stacks 30. The gate stacks 30 generally include a first insulating layer 30a, which serves as the gate oxide layer. A layer of conductive material 30b, which serves as the gate electrode, is deposited over the first insulating layer 30a. A gate stack insulating layer 30c is deposited over the gate electrode 30b. Additionally, the gate stacks 30 can include layers of high conductivity material between the gate electrode 30b and the gate stack insulating layer 30c, such as a silicide layer or a barrier layer and a refractory metal layer. Dark current, however, can increase dramatically when such highly conductive materials are included in the gate stacks 30 of a pixel cell 10.
It is desirable to have a pixel cell including low resistance conductors that would not result in increased dark current.